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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
ADM1276
OV
VCAP
ISET
SS
TIMER
1
2
3
4
5
INDICATOR
ADM1276-3
TOP VIEW
(Not to Scale)
15 GND
14 VOUT
13 FLB
12 PWRGD
11 SCL
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE BOARD TO IMPROVE THERMAL
DISSIPATION. THE EXPOSED PADDLE
CAN BE CONNECTED TO GROUND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
VCC
UV
OV
VCAP
ISET
SS
TIMER
LATCH
ADR
ENABLE
GPO2/ALERT2
SDA
SCL
PWRGD
FLB
Description
Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is
detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain
greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required.
Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
Internal Regulated Supply. Place a capacitor with a value of 1 μF or greater on this pin to maintain good
accuracy. This pin can be used as a reference to program the ISET pin voltage.
Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls
the current sense voltage limit, which controls the inrush current profile.
Timer Pin. An external capacitor, C TIMER , sets an initial timing cycle delay and a fault delay. The GATE pin is pulled
low when the voltage on the TIMER pin exceeds the upper threshold.
Latch Pin. This pin signals that the device is latching off after an overcurrent fault. The device can be configured
for automatic retry after latch-off by connecting this pin directly to the UV or the ENABLE pin.
PMBus Address Pin. This pin can be tied to GND, tied to VCAP, remain floating, or tied low through a resistor to
set four different PMBus addresses (see the Device Addressing section).
Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1276 hot swap controller to
begin a power-up sequence. If this pin is held low, the ADM1276 is prevented from powering up. There is no
internal pull-up on this pin.
General-Purpose Digital Output/Alert. This is a dual function pin. There is no internal pull-up on this pin. The
ALERT2 function of this pin can be configured to generate an alert signal when one or more fault or warning
conditions are detected. At power-up, ALERT2 indicates the FET health mode by default.
Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up.
Serial Clock Pin. Open-drain input. Requires an external resistive pull-up.
Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage
present on the FLB pin.
Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce
the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is
not increased beyond the SOA limits.
Rev. C | Page 9 of 48
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